CDCLVD2106
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SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011
Dual 1:6 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD2106
FEATURES
1
• Dual 1:6 Differential Buffer • Low Additive Jitter: 300 fs rms
in 10 kHz – 20 MHz • Low Within Bank Output Skew of 45 ps (Max) • Universal Inputs Accept LVDS, LVPECL,
LV
CMOS • One Input Dedicated for Six Outputs • Total of 12 LVDS Outputs, ANSI EIA/TIA-644A
Standard Compatible • Clock Frequency up to 800 MHz • 2.
375–2.
625 V Device Power Supply • LVDS Reference
Voltage, VAC_REF, Available for
Capacitive Coupled Inputs • Industrial Temperature Range –40°C to 85°C • Packaged in 6 mm x 6 mm 40-pin QFN (RHA) • ESD Protection Exceeds 3-kV HB...