CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002
D Low-Output Skew for Clock-Distribution
Applications
D Differential Low-
Voltage Pseudo-ECL
(LVPECL) Compatible Inputs and Outputs
D Distributes Differential Clock Inputs to Nine
Differential Clock Outputs
D Output Reference
Voltage (VREF ) Allows
Distribution From a Single-Ended Clock Input
D Packaged In a 28-Pin Plastic Chip Carrier
description
The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN) to nine pairs of differential clock (Y, Y) outputs with minimum skew for clock distribution.
It is specifically designed for driving 50-Ω tr...