CY26049-22 FailSafe™ PacketClock™ Global Communications Clock Generator Features • Fully integrated phase-locked loop (PLL) • FailSafe output • PLL driven by a crystal oscillator that is phase aligned with external reference • 100-MHz output from 10-MHz input • Low-jitter, high-accuracy outputs • 3.
3V ± 5% operation • 16-lead TSSOP Benefits • Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components • When reference is off, DCXO maintains clock outputs and SAFE pin indicates FailSafe conditions • DCXO maintains continuous operation should the input reference clock fail • Glitch-free transition simplifies sys...

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