Part Number
|
CY2SSTV855 |
Manufacturer
|
Cypress Semiconductor |
Description
|
Differential Clock Buffer/Driver |
Published
|
Feb 23, 2008 |
Detailed Description
|
www.DataSheet4U.com
CY2SSTV855
Differential Clock Buffer/Driver
Features
• Phase-locked loop (PLL) clock distribution ...
|
Datasheet
|
CY2SSTV855
|
Overview
www.
DataSheet4U.
com
CY2SSTV855
Differential Clock Buffer/Driver
Features
• Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input • SSCG: Spread Aware™ for electromagnetic interference (EMI) reduction • 28-pin TSSOP package • Conform to JEDEC DDR specifications
Functional Description
The CY2SSTV855 is a high-performance, very-low-skew, very-low-jitter zero-delay buffer that distributes a differential clock input pair (SSTL_2) to four differential (SSTL_2) pairs of clock outputs and one differential pair of feedback clock outputs.
...
Similar Datasheet