CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K × 18 common I/O architecture • 3.
3V core power supply (VDD) • 2.
5V/3.
3V I/O power supply (VDDQ) • Fast clock-to-output times — 3.
5 ns (for 166-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Available in JEDEC-standard lead-free 100-Pin TQFP package • “ZZ” Sleep Mode Option Functional Description[1] The CY7C1212H SRAM integrates 64K x ...

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