Part Number
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CY7C1412KV18 |
Manufacturer
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Cypress Semiconductor |
Description
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36-Mbit QDR II SRAM Two-Word Burst Architecture |
Published
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Mar 14, 2017 |
Detailed Description
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CY7C1425KV18 CY7C1412KV18 CY7C1414KV18
36-Mbit QDR® II SRAM Two-Word Burst Architecture
36-Mbit QDR® II SRAM Two-Word B...
|
Datasheet
|
CY7C1412KV18
|
Overview
CY7C1425KV18 CY7C1412KV18 CY7C1414KV18
36-Mbit QDR® II SRAM Two-Word Burst Architecture
36-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems ■ Single multiplexed address input bus latches a...
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