144-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1668KV18 CY7C1670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ 144-Mbit density (8 M × 18, 4 M × 36) ■ 550-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data trans...
Cypress Semiconductor