144-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C2670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features ■ 144-Mbit density (4 M × 36) ■ 550-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferre...
Cypress Semiconductor