June 2006, ver.
3.
5
®
MAX 3000A
Programmable Logic Device Family
Data Sheet
Features.
.
.
■ High–performance, low–cost
CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1)
■ 3.
3-V in-system programmability (ISP) through the built–in IEEE Std.
1149.
1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ISP circuitry compliant with IEEE Std.
1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std.
1149.
1-1990
■ Enhanced ISP features: – Enhanced ISP algorithm for faster programming – ISP_Done bit to ensure complete programming – Pull-up resistor on I/O pins during in–system programming
■ High–density PLDs ...