HEF4040B-Q100 12-stage binary ripple counter Rev.
1 — 4 April 2013 Product data sheet 1.
General description The HEF4040B-Q100 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11).
The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP.
Each counter stage is a static toggle flip-flop.
The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground).
Unused inputs mu...

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