HI-6110
November 2006
MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
FEATURES
• • • • • • • Monolithic
CMOS technology 3.
3V operation Exceptionally low power On-chip message buffering Selectable master clock frequency Dual differential 1553 bus transceivers Bus Controller / Remote Terminal / Monitor Terminal operating modes • Compliant to MIL-STD-1553B Notice 2 and MIL-STD-1760 Stores Management
GENERAL DESCRIPTION
The HI-6110 is a
CMOS integrated circuit implementing the MIL-STD-1553 (1553) data communications protocol between a host processor and a dual redundant 1553 data bus.
The single chip architecture has a digital section containing all necessary logic and memory to pro...