w e e Document h Title S / 256Mx16bit) NAND Flash Memory 4Gbit (512Mx8bit a at .
D History Revision w w Revision No.
0.
0 U 4 t .
m o c Preliminary HY27UG(08/16)4G(2/D)M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash History Draft Date May.
13.
2005 Remark Preliminary Initial Draft.
1) Add Errata tWH tWP 25 35 tWC 50 60 0.
1 Specification Relaxed value 15 20 May.
23.
2005 1) Correct the Valid Blocks Number.
0.
2 Valid Blocks (max) Before After 4,098 4,096 1) Add tRSBY (Table 11) - tRSBY (Dummy Busy Time for Cache Read) 0.
3 - tRSBY is 5us (typ.
) 2) Edit Figure 18, 19 1) Add ULGA Package.
3) Correct Extended Read Status Register Commands (Table.
19) - Figures & texts are added.
...

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