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HY57V561620C(L)T(P)
4 Banks x 4M x 16Bit Synchronous DRAM
DESCRIPTION
The HY57V561620C(L)T(P) Series is a 268,435,456bit
CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.
HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16.
HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock.
All inputs and outputs are synchronized with the rising edge of the clock input.
The data paths are internally pipelined to achieve very high bandwidth.
All input and output
voltage levels are compatible with LVTTL.
Programmable options include the lengt...