Part Number
|
IDTS3 |
Manufacturer
|
AMI |
Description
|
CMOS Gate Array |
Published
|
Mar 12, 2018 |
Detailed Description
|
,'76
®
Description IDTS3 is a non-inverting, TTL-level Schmitt input buffer piece.
Logic Symbol
Truth Table
IDTS3
Q...
|
Datasheet
|
IDTS3
|
Overview
,'76
®
Description IDTS3 is a non-inverting, TTL-level Schmitt input buffer piece.
Logic Symbol
Truth Table
IDTS3
QC P PADM D
PADM QC LL HH
$0,+* PLFURQ &026 *DWH $UUD\
Pin Loading
PADM
Load 4.
90 pF
HDL Syntax Verilog IDTS3 inst_IDTS3 (QC, PADM); VHDL.
.
inst_IDTS3 : IDTS3 port map (QC, PADM);
Power Characteristics
Parameter Static IDD (TJ = 85°C) EQLpd
See page 2-15 for power equation.
Value TBD 15.
8
Units nA Eq-load
Propagation Delays Conditions: TJ = 25°C, VDD = 5.
0V, Typical Process
Delay (ns) From
To
Parameter
1
PADM
QC
tPLH tPHL
0.
99 1.
72
Delay will vary with input conditions.
See page 2-17 for interconnect estimates...
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