,'7; $0,+*  PLFURQ &026 *DWH $UUD\ Description IDTX3 is a non-inverting, TTL-level, input buffer piece.
Logic Symbol Truth Table IDTX3 QC P PADM D PADM QC LL HH ® Pin Loading Load PADM 4.
90 pF HDL Syntax Verilog .
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IDTX3 inst_name (QC, PADM); VHDL.
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inst_name: IDTX3 port map (QC, PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation.
Value TBD 10.
4 Units nA Eq-load Input Propagation Delays Conditions: TJ = 25°C, VDD = 5.
0V, Typical Process Delay (ns) From To Parameter 1 PADM QC tPLH tPHL 0.
53 0.
72 Delay will vary with input conditions.
See page 2-17 for interconnect estimates.
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