com IP100A LF Preliminary Data Sheet Integrated 10/100 Ethernet MAC + PHY Features Single chip 10/100BASE, half or full duplex Ethernet Media Access Controller IEEE 802.
3 compliant 100BASE-TX/100BASE-FX/10BASE-T PCI Bus master scatter/gather DMA on any byte boundary Full operation with PCI Clock from 25 MHz to 33 MHz PCI Revision 2.
2 compliant On-chip transmit and receive FIFO buffers On-chip LED drivers Power management capabilities for ACPI 1.
0 compliant systems WakeOnLAN support Management statistics gathering IP multicast receive and filter support using 64 bit hash table Transmit polling Auto pad insertion for short packets Programmable minimum Inter Packet Gap Support...

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