| Part Number | IS61QDPB44M18A |
| Manufacturer | ISSI |
| Title | 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM |
| Description | at page 6 for each ODT option. DESCRIPTION The 72Mb IS61QDPB42M36A/A1/A2 and IS61QDPB44M18A/A1/A2 are synchronous, highperformance CMOS static ra... |
| Features |
2Mx36 and 4Mx18 configuration available. On-chip Delay Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write... |
| File Size | 698.51KB |
| Datasheet |
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IS61QDPB44M18C2 : IS61QDPB44M18C/C1/C2 IS61QDPB42M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) APRIL 2019 FEATURES 2Mx36 and 4Mx18 configuration available. Separate independent read and write ports with concurrent read and write operations. Max. 567 MHz clock for high bandwidth Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. DESCRIPTION The 72Mb IS61QDPB42M36C/C1/C2 and IS61QDPB44M18 C/C1/C2 are synchronous, high-performance CMOS static random access memo.
IS61QDPB44M18C1 : IS61QDPB44M18C/C1/C2 IS61QDPB42M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) APRIL 2019 FEATURES 2Mx36 and 4Mx18 configuration available. Separate independent read and write ports with concurrent read and write operations. Max. 567 MHz clock for high bandwidth Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. DESCRIPTION The 72Mb IS61QDPB42M36C/C1/C2 and IS61QDPB44M18 C/C1/C2 are synchronous, high-performance CMOS static random access memo.
IS61QDPB44M18C : IS61QDPB44M18C/C1/C2 IS61QDPB42M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) APRIL 2019 FEATURES 2Mx36 and 4Mx18 configuration available. Separate independent read and write ports with concurrent read and write operations. Max. 567 MHz clock for high bandwidth Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. DESCRIPTION The 72Mb IS61QDPB42M36C/C1/C2 and IS61QDPB44M18 C/C1/C2 are synchronous, high-performance CMOS static random access memo.
IS61QDPB44M18B2 : IS61QDPB44M18B/B1/B2 IS61QDPB42M36B/B1/B2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) DECEMBER 2015 FEATURES 2Mx36 and 4Mx18 configuration available. On-chip Delay Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simult.
IS61QDPB44M18B1 : IS61QDPB44M18B/B1/B2 IS61QDPB42M36B/B1/B2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) DECEMBER 2015 FEATURES 2Mx36 and 4Mx18 configuration available. On-chip Delay Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simult.