IS61S6432 ISSI® 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM JUNE 2001 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 100-Pin TQFP and PQFP package • Single +3.
3V power supply • Two Clock enables and one Clock disable to eliminate multiple bank bus contention • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be conn...

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