ISB35000 SERIES
H
CMOS STRUCTURED ARRAY
PRELIMINARY DATA
FEATURES 0.
5 micron triple layer metal H
CMOS process featuring retrograde well technology, low resistance salicided active areas, polysilicide gates and thin metal oxide.
3.
3 V optimized transistor with 5 V I/O interface capability 2 - input NAND delay of 0.
210 ns (typ) with fanout = 2.
Broad I/O functionality including LV
CMOS, LVTTL, GTL, PECL, and LVDS.
High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike suppression and impedance matching.
Metallised generators to support SPRAM and DPRAM, plus an extensive embedded function library.
Combines Standard Cell Features with Sea of Gates time to market.
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