K4S281632C-TI(P)
CMOS SDRAM
128Mbit SDRAM
2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.
1 June 2001
* Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
1 Jun.
2001
K4S281632C-TI(P)
Revision History
Revision 0.
0 (November 18, 2000)
• First generation.
CMOS SDRAM
Revision 0.
1 (June 20, 2001)
• Final Specification.
Rev.
0.
1 Jun.
2001
K4S281632C-TI(P)
2M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.
3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Inte...