KM416S4030C
Revision History
Revision 1 (May 1998)
- ICC2 N value (10mA) is changed to 12mA.
Preliminary
CMOS SDRAM
Revision .
2 (June 1998)
- tSH (-10 binning) is revised.
REV.
2 June '98
KM416S4030C
1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• • • • JEDEC standard 3.
3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle)
Preliminary
CMOS SDRAM
GENER...