Product Folder Order Now Technical Documents Tools & Software Support & Community LMK04821, LMK04826, LMK04828 SNAS605AS – MARCH 2013 – REVISED MAY 2020 LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs 1 Features •1 JEDEC JESD204B Support • Ultra-Low RMS Jitter – 88 fs RMS Jitter (12 kHz to 20 MHz) – 91 fs RMS Jitter (100 Hz to 20 MHz) – –162.
5 dBc/Hz Noise Floor at 245.
76 MHz • Up to 14 Differential Device Clocks from PLL2 – Up to 7 SYSREF Clocks – Maximum Clock Output Frequency 3.
1 GHz – LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2 • Up to 1 Buffered VCXO/Crystal Output from PLL1 – LVPECL, LVDS, 2xLVCMOS Programmable • Dual Loop PLLati...

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