LP61L256C
Preliminary
Document Title 32K X 8 BIT HIGH SPEED
CMOS SRAM Revision History
Rev.
No.
0.
0
32K X 8 BIT HIGH SPEED
CMOS SRAM
History
Initial issue
Issue Date
November 9, 2001
Remark
Preliminary
PRELIMINARY
(November, 2001, Version 0.
0)
AMIC Technology, Inc.
LP61L256C
Preliminary
Features
n Single +3.
3V power supply n Access times: 12/15 ns (max.
) n Current: Operating: 120mA (max.
) Standby: 5mA (max.
) n Full static operation, no clock or refreshing required n n n n All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention
voltage: 2V (min.
) Available in 28-pin SOJ package
32K X 8 BIT HIGH SPEED
CMOS SRAM
General Description
The LP6...