Part Number
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M15F5121632A |
Manufacturer
|
ESMT |
Description
|
DDR3 SDRAM |
Published
|
Sep 20, 2018 |
Detailed Description
|
ESMT
DDR3 SDRAM
(Preliminary)
Feature
Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) JEDEC DDR3 Compli...
|
Datasheet
|
M15F5121632A
|
Overview
ESMT
DDR3 SDRAM
(Preliminary)
Feature
Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.
5V(±0.
075V) JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe
(DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM
Data Integrity ˗ Auto Refresh and Self Refresh Modes
Power Saving Mode ˗ Partial Array Self Refresh(PASR) ˗ Power Down Mode
Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
M15F5121632A
4M x 16 Bit x 8 Banks DDR3 SDRAM
˗ Write Leveling via MR settings ˗ Read Leveling via MPR Programmable Functions ˗ ...
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