Part Number
|
M5M5Y5672TG-25 |
Manufacturer
|
Mitsubishi |
Description
|
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
Published
|
Apr 26, 2005 |
Detailed Description
|
2001.May Rev.0.1
MITSUBISHI LSIs
Advanced Information
Notice: This is not final specification. Some parametric limits ...
|
Datasheet
|
M5M5Y5672TG-25
|
Overview
2001.
May Rev.
0.
1
MITSUBISHI LSIs
Advanced Information
Notice: This is not final specification.
Some parametric limits are subject to change.
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#, BWg#, BWh#), Echo Clock outputs (CQ1, CQ1#, CQ2, CQ2#) and Read/Write (W#).
Write operations are controlled by the eight Byte Write Enables (BWa# - BWh#) and Read/Write(W#) inputs.
All writes are conducte...
Similar Datasheet