M68AR512D
8 Mbit (512K x16) 1.
8V Asynchronous SRAM
FEATURES SUMMARY s SUPPLY
VOLTAGE: 1.
65 to 1.
95V
s s s s s s s s
Figure 1.
Packages
512K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.
0V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN DUAL CHIP ENABLE for EASY DEPTH EXPANSION
BGA
BGA
TFBGA48 (ZB) 6 x 7mm
TFBGA48 (ZB) 8 x 10mm
October 2002
1/19
M68AR512D
TABLE OF CONTENTS SUMMARY DESCRIPTION .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3 Figure 2.
Logic Diagram .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
...