MACH 1 and 2 CPLD Families
High-Performance EE
CMOS Programmable Logic
FEATURES
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High-performance electrically-erasable
CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages SpeedLocking™ – guaranteed fixed timing up to 16 product terms Commercial 5/5.
5/6/7.
5/10/12/15-ns tPD and Industrial 7.
5/10/12/14/18-ns tPD Configurable macrocells — Programmable polarity — Registered or combinatorial outputs — Internal and I/O feedback paths — D-type or T-type flip-flops — Output Enables — Choice of clocks for each flip-flop — Input registers for MACH 2 family JTAG (IEEE 1149.
1)-compatible, 5-V in-system programming available Peripher...