High-Density EE CMOS Programmable Logic
FINAL COM’L: -10/15/20 IND: -18/24 MACH230-10/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 128 Macrocells 10 ns tPD Commercial 18 ns tPD Industrial 100 MHz fCNT 70 Inputs 64 Outputs Lattice Semiconductor 128 Flip-flops; 4 clock choices 8 “PAL26V16” blocks with buried macrocells Pin-compatible with MACH130, MACH131, M...
Lattice