19-3259; Rev 0; 5/04
KIT ATION EVALU E L B AVAILA
40Msps, 12-Bit ADC
General Description Features
o Excellent Dynamic Performance 68.
6dB SNR at fIN = 20MHz 90dBc SFDR at fIN = 20MHz o Low-Power Operation 159mW at 3.
0V (Single-Ended Clock) 181mW at 3.
3V (Single-Ended Clock) 198mW at 3.
3V (Differential Clock) o Differential or Single-Ended Clock o Accepts 20% to 80% Clock Duty Cycle o Fully Differential or Single-Ended Analog Input o Adjustable Full-Scale Analog Input Range o Common-Mode Reference o Power-Down Mode o
CMOS-Compatible Outputs in Two’s Complement or Gray Code o Data-Valid Indicator Simplifies Digital Design o Out-of-Range and Data-Valid Indicators o Miniature, 40-Pin Thin QFN P...