3.
3 V LVTTL/LV
CMOS to LVPECL Translator
MC100EPT622
Description The MC100EPT622 is a 10−Bit LVTTL/LV
CMOS to LVPECL
translator.
Because LVPECL (Positive ECL) levels are used only +3.
3 V and ground are required.
The device has an OR−ed enable input which can accept either LVPECL (ENPECL) or TTL/LV
CMOS inputs (ENTTL).
If the inputs are left open, they will default to the enable state.
The device design has been optimized for low channel−to−channel skew.
Features
• 450 ps Typical Propagation Delay • Maximum Frequency 1.
5 GHz Typical • PECL Mode • Operating Range: VCC = 3.
0 V to 3.
8 V with VEE = 0 V • PNP LVTTL Inputs for Minimal Loading • Q Output Will Default HIGH with Inputs Open • The 100 ...