MM74HC139 Dual 2-To-4 Line Decoder
September 1983 Revised February 1999
MM74HC139 Dual 2-To-4 Line Decoder
General Description
The MM74HC139 decoder utilizes advanced silicon-gate
CMOS technology, and is well suited to memory address decoding or data routing applications.
It possesses the high noise immunity and low power consumption usually associated with
CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic.
The MM74HC139 contain two independent one-of-four decoders each with a single active low enable input (G1, or G2).
Data on the select inputs (A1, and B1 or A2, and B2) cause one of the four normally high outputs to go LOW.
The decoder’s outputs can drive 10 low p...