| Part Number | MT9072 |
| Manufacturer | Zarlink Semiconductor |
| Title | Octal T1/E1/J1 Framer |
| Description | The MT9072 is a multi-port T1/E1/J1 framing device that integrates eight fully independent, feature rich framers. The device is software selectabl... |
| Features |
• • • • Eight fully independent, T1/E1/J1 framers 3.3 V supply with 5 V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes: - T1: D4, ESF, T1DM - E1: Basic Framing, CRC4 multiframing and Signaling Multiframing Supports Inverse Mux for ATM T... |
| File Size | 3.65MB |
| Datasheet |
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MT9079 : ® CMOS ST-BUS™ FAMILY MT9079 Advanced Controller for E1 Features • Meets applicable requirements of CCITT G.704, G.706, G.732, G.775, G.796, I.431 and ETSI ETS 300 011 HDB3, RZ, NRZ (fibre interface) and bipolar NRZ line codes Data link access and national bit buffers (five bytes each) Enhanced alarms, performance monitoring and error insertion Maskable interrupts for alarms, receive CAS bit changes, exception conditions and counter overflows Automatic interworking between CRC-4 and non-CRC-4 multiframing Dual transmit and receive 16 byte circular channel buffers Two frame receive elastic buffer with controlled slip direction indication and 26 channel hysteresis (208 UI wander tolerance) C.
MT9076 : MT9076 T1/E1/J1 3.3V Single Chip Transceiver Preliminary Information Features • • Combined T1/E1/J1 framer and LIU, with PLL and 3 HDLCs In T1/J1 mode the LIU can recover signals attenuated by up to 43dB (7000ft of 22 AWG cable) In E1 mode the LIU can recover signals attenuated by up to 43dB (2200m of 0.65mm cable) Low jitter digital PLL (intrinsic jitter 0.02UI) HDLCs can be assigned to any timeslot Comprehensive alarm detection, performance monitoring and error insertion functions 2.048Mbit/s or 8.192Mbit/s ST-BUS streams Support for Inverse Mux for ATM (IMA) Support for V5.1 and V5.2 Access Networks 3.3V operation with 5V tolerant inputs Intel or Motorola non-multiplexed 8-bit microproc.
MT9075B : www.DataSheet4U.com MT9075B E1 Single Chip Transceiver Data Sheet Features • Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package Selectable bit rate data link access with optional Sa bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1) LIU dynamic range of 20 dB Enhanced performance monitoring and programmable error insertion functions Low jitter DPLL for clock generation Operating under synchronized or free run mode Two-frame receive elastic buffer with controlled slip direction indication Selectable transmit or receive jitter attenuator Intel or Motorola non-multiplexed parallel microprocessor interface CRC-4 updat.
MT9075B : MT9075B E1 Single Chip Transceiver Preliminary Information Features • Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package Selectable bit rate data link access with optional S a bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1) LIU dynamic range of 20 dB Enhanced performance monitoring and programmable error insertion functions Low jitter DPLL for clock generation Operating under synchronized or free run mode Two-frame receive elastic buffer with controlled slip direction indication Selectable transmit or receive jitter attenuator Intel or Motorola non-multiplexed parallel microprocessor interface CRC-4 updating alg.
MT9075A : MT9075A E1 Single Chip Transceiver Preliminary Information Features • Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package Selectable bit rate data link access with optional S a bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1) Enhanced performance monitoring and programmable error insertion functions Low jitter DPLL for clock generation Operating under synchronized or free run mode Two-frame receive elastic buffer with controlled slip direction indication Selectable transmit or receive jitter attenuator Intel or Motorola non-multiplexed parallel microprocessor interface CRC-4 updating algorithm for intermediate pa.