NB3N853501E
3.
3 V LVTTL/LV
CMOS 2:1 MUX to 4 LVPECL Differential Clock Fanout Buffer Outputs with Clock Enable and Clock Select
Description The NB3N853501E is a pure 3.
3 V supply 2:1:4 clock distribution
fanout buffer.
Input MUX selects one of two LV
CMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LV
CMOS/LVTTL levels.
Outputs are LVPECL levels and are synchronously enabled by CLK_EN using LV
CMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).
Features
• Four differential LVPECL Outputs • Two Selectable LV
CMOS/LVTTL CLOCK Inputs • Up to 266 MHz Clock Operation • Output to Output Skew: 30 ps (Max.
) • Device to Device Skew 250 ps (Max.
) • Propagation Del...