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Description ODCSXXxx is a family of 4 to 24 mA, non-inverting,
CMOS-level, output buffer pieces with controlled slew rate outputs.
Logic Symbol
Truth Table
ODCSXXxx
SL
A PADM
A PADM LL HH
HDL Syntax Verilog ODCSXXxx inst_name (PADM, A); VHDL.
.
inst_name: ODCSXXxx port map (PADM, A);
Pin Loading
Pin Name A (eq-load)
ODCSXX04 9.
3
Power Characteristics
Cell Output Drive (mA)
ODCSXX04
4
ODCSXX08
8
ODCSXX12
12
ODCSXX16
16
ODCSXX24
24
a.
See page 2-15 for power equation.
ODCSXX08 9.
3
Load ODCSXX12
9.
3
ODCSXX16 9.
3
Power Characteristicsa
Static IDD (TJ = 85°C) (nA) TBD
EQLpd (Eq-load) ...