Deutron Electronics Corp.
P2S28D30/40CTP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice.
DESCRIPTION P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.
All control and address signals www.
DataSheet4U.
com are referenced to the rising edge of CLK.
Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK.
The P2S28D30/40CTP achieves very high speed clock rate up to 200 MHz .
FEATURES - Vdd=Vddq=2.
5V+0.
2V - Double data rate architecture ; two data transfers per clock...

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