Features
• • • • • • • • • • • • • • • • •
3000 Dhrystone 2.
1 MIPS at 1.
3 GHz Selectable Bus Clock (30 CPU Bus Dividers up to 28x) 13 Selectable Core-to-L3 Frequency Divisors Selectable MPx/60x Interface
Voltage (1.
8V, 2.
5V) Selectable L3 Interface of 1.
8V or 2.
5V PD Typical 12.
6W at 1 GHz at VDD = 1.
3V; 8.
3W at 1 GHz at VDD = 1.
1V, Full Operating Conditions Nap, Doze and Sleep Modes for Power Saving Superscalar (Four Instructions Fetched Per Clock Cycle) 4 GB Direct Addressing Range Virtual Memory: 4 Hexabytes (252) 64-bit Data and 32-bit Address Bus Interface Integrated L1: 32 KB Instruction and 32 KB Data Cache Integrated L2: 512 KB 11 Independent Execution Units and Three Register Files ...