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Features
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3000 Dhrystone 2.
1 MIPS at 1.
3 GHz Selectable Bus Clock (30 CPU Bus Dividers up to 28x) Selectable MPx/60x Interface
Voltage (1.
8V, 2.
5V) PD Typically 18W at 1.
33 GHz at VDD = 1.
3V; 8.
0W at 1 GHz at VDD = 1.
1V Full Operating Conditions Nap, Doze and Sleep Power Saving Modes Superscalar (Four Instructions Fetched Per Clock Cycle) 4 GB Direct Addressing Range Virtual Memory: 4 Hexabytes (252) 64-bit Data and 36-bit Address Bus Interface Integrated L1: 32 KB Instruction and 32 KB Data Cache Integrated L2: 512 KB 11 Independent Execution Units and 3 Register Files Write-back and Write-through Operations fINT Max = 1.
33 GHz (1.
42 GHz to ...