m o .
c U 4 t e FEATURES e h • Full
CMOS output swing with 40-mA output drive S output capability.
25-mA drive at TTL level.
a t • Advanced, low power, sub-micron
CMOS processes.
a • 25MHz .
D fundamental crystal or clock input.
• 4 outputs fixed at 50MHz with output disable, 1 output w selectable at 25MHz or 100MHz with output disable w • SDRAM selectable frequencies of 66.
6, 75, 83.
3, 100MHz w (Double Drive Strength).
• • • •
•
PLL650-03
Low EMI Network LAN Clock
PIN CONFIGURATION
XIN XOUT/50MHz_OE*^ GND VDD 1 2 16 15 VDD VDD 25MHz/100MHz GND GND SDRAMx2 VDD 50MHz/SS0*
T
PLL 650-03
3 4 5 6 7 8
14 13 12 11 10 9
Spread spectrum technology selectable for EMI reduction from ±0.
5%, ±0.
75% ce...