FEATURES
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Full
CMOS output swing with 40-mA output drive capability.
25-mA output drive at TTL level.
Advanced, low power, sub-micron
CMOS processes.
25MHz fundamental crystal or clock input.
One output fixed at 50MHz One selectable frequency output of 66.
6 or 75MHz (with Double Drive Strength output).
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.
3V operation.
Available in 8-Pin 150mil SOIC.
.
D
at
h S a
t e e
4U
.
m o c
PLL650-06
Network LAN Clock
PIN CONFIGURATION
XIN XOUT GND 50MHz/FS* 1 2 3 4 8 7 6 5 VDD GND 75MHz+/66MHz+ VDD
PLL650-06
*: bi-directional pin
+ : double strength output
FREQUENCY TABLE
FS
DESCRIPTIONS
The PLL 65...