FEATURES
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Full
CMOS output swing with 40-mA output drive capability.
25-mA output drive at TTL level.
Advanced, low power, sub-micron
CMOS processes.
25MHz fundamental crystal or clock input.
1 output fixed at 100MHz , 1 output fixed at 125MHz .
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.
3V operation.
Available in 8-Pin 150mil SOIC.
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PRELIMINARY
PLL650-08
Network LAN Clock Source
PIN CONFIGURATION
XIN XOUT GND VDD
1 2 3 4
8 7 6 5
VDD 100MHz GND 125MHz
PLL 650-08
DESCRIPTIONS
The PLL 650-08 is a low cost, low jitter, and high performance clock synthesizer.
With PhaseLink’s proprietary analog Phase Lock...