SEMD6
NPN/PNP Silicon Digital Transistor Array Preliminary data • Switching circuit, inverter, interface circuit, driver circuit • Two (galvanic) internal isolated NPN/PNP Transistors in one package • Built in bias resistor (R1=4.
7kΩ) Tape loading orientation
C1 B2 5 E2 4
4 5 3 6 1 2
Top View
3 2 1
Marking on SOT666 package (for example W R) corresponds to pin 1 of device Position in tape: pin 1 same of feed hole side
6
R1 TR1
R1 TR2
4 5 6
Direction of Unreeling
Type SEMD6
Maximum Ratings Parameter
Collector-emitter
voltage Collector-base
voltage Emitter-base
voltage Input on
Voltage DC collector current Total power dissipation, TS = 75 °C Junction temperature Storage temperature
T...