D Members of the Texas Instruments
Widebus™ Family
D State-of-the-Art EPIC-ΙΙB™ Bi
CMOS Design
Significantly Reduces Power Dissipation
D Typical VOLP (Output Ground Bounce) 1 V
at VCC = 5 V, TA = 25°C
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Latch-Up Performance Exceeds 500 mA
Per JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil ...