D Members of the Texas Instruments
Widebus™ Family
D State-of-the-Art EPIC-ΙΙB™ Bi
CMOS Design
Significantly Reduces Power Dissipation
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D High-Impedance State During Power Up
and Power Down
D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Package Options Include Plastic Thin
Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
description
The ’ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-imp...