D Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
D State-of-the-Art EPIC-ΙΙB™ Bi
CMOS Design
Significantly Reduces Power Dissipation
D Typical VOLP (Output Ground Bounce) 1 V
at VCC = 5 V, TA = 25°C
D Latch-Up Performance Exceeds 500 mA
Per JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
2Y4 1A1 1OE VCC 2OE
SN54ABT2240A, SN74ABT2240A OCTAL BUFFERS AND LINE/MO...