• Designed to Ensure Defined
Voltage Levels
on Floating Bus Lines in
CMOS Systems
• Reduces Undershoot and Overshoot
Caused By Line Reflections
• Repetitive Peak Forward
Current .
.
.
IFRM = 100 mA
• Inputs Are TTL-
Voltage Compatible • Low Power Consumption (Like
CMOS) • ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
• Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
SN74ACT1071 10-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993
D PACKAGE (TOP VIEW)
D1 1 D2 2 GND 3 GND 4 D3 5 D4 6 D5 7
14 D10 13 D9 12 D8 11 VCC 10 VCC 9 D7 8 D6
description
This de...