SPEAR-09-B042 SPEAr® BASIC ARM 926EJ-S core, customizable logic, large IP portfolio SoC Preliminary Data Features ■ ■ ARM926EJ-S core @333 MHz – 16 Kbyte instructions/data cache Reconfigurable logic array: – 300 Kgate (100% utilization rate) – 102 I/O lines – No clock domain limitation – 64 Kbyte + 8 Kbyte configurable memory pool Multilayer AMBA 2.
0 compliant bus with fMAX 166 MHz 32-Kbyte boot ROM 8 Kbyte common static RAM – Shared with reconfigurable array Dynamic power saving features High performance DMA – 8 channels Ethernet 10/100 MAC with MII interface.
(IEEE-802.
3) USB 2.
0 device with integrated PHY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LFBGA289 6 legacy GPIO bidirectional signals with inter...

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