STA240 Sirius SDARS channel, service & source decoder Data Brief Features ■ 2 Satellite and 1 terrestrial signal demodulators com and decoders ■ ■ Advanced DSP processor to implement PAC audio decoder Requires a single 17MHz clock reference; all high-speed clock signals are derived using on-chip PLL Programmable I2S to support 32K/48K/44.
1K audio sample rate (32K/48K Sample rates use internal clocks, 44.
1K Sample rate uses external clock) I2C master interface to control tuner and audio DAC External control through uart interface using sirius standard protocol (SSP) over RS-232 LBGA288 ■ ■ ■ Description STA240 is a fully integrated 3rd generation Baseband signal processor...

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)