Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Features
s 5 V only
s Low-power, latch-up-free
CMOS technology: — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation
s Fixed master clock frequency: 2.
048 MHz
s On-chip sample and hold, autozero, and precision
voltage reference
s Differential architecture for high noise immunity and power supply rejection
s PCM interface: — Fixed 2.
048 MHz data rate — Delayed and nondelayed PCM modes — Fully flexible time-slot assignment — Transmit and receive aligned or offset
s Transmit PCM data output enable
s Serial control interface with controlling processor
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