0
R XC2C512 CoolRunner-II CPLD
DS096 (v3.
2) March 8, 2007
00
Features
• Optimized for 1.
8V systems - As fast as 7.
1 ns pin-to-pin delays - As low as 14 μA quiescent current
• Industry’s best 0.
18 micron
CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-
voltage I/O operation — 1.
5V to 3.
3V
• Available in multiple package options - 208-pin PQFP with 173 user I/O - 256-ball FT (1.
0mm) BGA with 212 user I/O - 324-ball FG (1.
0mm) BGA with 270 user I/O - Pb-free available for all packages
• Advanced system features - Fastest in system programming · 1.
8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.
1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - U...