0
R
XCR3064XL 64 Macrocell CPLD
0 14
DS017 (v1.
6) January 8, 2002
Product Specification
Features
• • • • • Lowest power 64 macrocell CPLD 6.
0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages • • 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin VQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with 3.
3V core supply Advanced 0.
35 micron five layer metal EEPROM process Fast Zero Power™ (FZP)
CMOS design technology In-system programming Predictable timing model Up to 23 available clocks per functi...